In recent times, computation, processing or analysis are being performed on an extremely large volume of data. with the innovations in the fields of technology and the internet, there is an increase in size and complexity of raw or unprocessed data. when traditional or conventional systems, processes or computes such ‘big data’, the efficiency, speed and scalability of the system are reduced drastically. applications such as image recognition, data centres, health disorder recognition, neuroprosthetics, etc require a faster, efficient, scalable and robust system to process such a huge volume of complex data. mostly, the conventional systems are based on bus-system architecture. it has certain bottlenecks that hamper the speed, efficiency and throughput of the system. since then, neuromorphic computing has been a topical subject in research to match the efficiency of the brain and mimic the various cognitive function carried out by the brain. systems based on neural networks process such data very efficiently at a higher speed. the hardware neurons in the spiking neural network need to be interconnected via an architecture for neuromorphic computation. to overcome the major bottlenecks faced in the traditional bus-system architectures, network-on-chip (noc) architecture has emerged to be advantageous over any conventional architectures. systems based on network-on-chip architecture have benefitted in terms of scalability, latency, and throughput. noc also increases the parallelism of such systems. the proposed work consists of neurons interconnected in a particular topology within the network-on-chip architecture to form a neural network for neuromorphic computation. several interconnections such as 2d mesh, 3d mesh and wireless interconnections of neurons are looked in the work for various intra-neuron and inter-neuron communications. the use of neural network based on noc architecture makes the system more efficient, scalable and faster than existing systems. parameters such as membrane potential, latency and interconnection within various layers of the spiking neural network with different synaptic probabilities and poisson rate are analysed in detail. the proposed system is synthesized at 28 nm cmos technology node, and the neurons in the system were interconnected in a hierarchical manner, which was evaluated in terms of throughput, latency and energy.