Over the years with the scaling in transistor device dimensions of planar integration by following moore’s law resulted in an increased power density which leads to performance degradation due to the thermal issues, also the lithographic challenges triggered by fine pitch wiring where its scaling is much higher in comparison to transistor device scaling results an increased complexity of on-chip communication and manufacturing cost for finer nodes. it resulted finding an alternate solutions in-terms of enhancing the system performance by improving the integration of multifunctional ics (packaging) instead of device scaling. among the advanced ic integration methods, three-dimensional heterogeneous integration with through-silicon via (tsv) technology showed great potential towards the system-level integration with an increased interconnect density in a smaller footprint. however, the heat mitigation across several dies remains a critical issue in this technology with the utilization of vertical dimension, and the distributed hotspots in 3d ic's generating heat-fluxes up-to hundreds of w/cm2 to few thousands of w/cm2. traditionally, to keep the desired minimal thermal resistance between chip to ambient, numerous solutions are suggested in terms of packaging and cooing technology. the majority of solutions are based on conductive heat management in combination with conventional air-cooled heat-sinks. however, the progress in device scaling, resulted in an increased bulkiness of the heat sink significantly in the same proportionate of the cooling of the processor, which confines efficiency the chip package and the system size. and also, the heat removing capacity of the conventional air-cooled heat sinks limite to a maximum heat flux of about ~100 w/cm2. however, to accomplish such hotspots, micro-fluidic cooling was recognized as a promising approach. in light of this, herein, we propose a facile approach of micro-fluidic integration in between stacked dies, which facilitates inter-die cooling. the integration achieved thru silicide (ti/si) assisted thermo-compression bonding and here, the bonding conditions were optimized and performed at low thermal budgets upon glass-silicon and silicon-silicon stacks. also, we demonstrated the fabrication of fine micro-channels (up to 100 µm with a pitch of 200 µm) over three-layer stacks and evaluated its tight sealing using liquid pumping. it gave us the motivation for visualization of such inter-die micro channel integration for the future high process computing applications. apart from this, the performed 200 µm width tightly sealed fine ring encapsulation study will be helpful for mems capping applications. also, the tightly sealed glass encapsulation of the microsystem can also be useful for several bio-sensing or chemical sensing applications by making novel nano dimensional micro-fluidic channels.